Exam text content

Name:
Student no.

Final Exam: Answer every guestion
2nd Midterm Exam: Answer only guestions 3-5

Made by: Arto Perttula

Students can use any calculator or dictionary.

Moreover, each student can have 1 A4 sheet of own notes. There are no restrictions
about their style and they are not collected.

Students can do anything they wish with the exam paper.

In addition to text, use figures, tables, eguations, and examples in your answers.

In logic diagrams, you can use basic gates (AND, OR...), flip-flops, multiplexers, and common
arithmetic components (adder, subtractor, multiplier, comparator...).

Mark the name of every signal and indicate their width clearly.

Preferably write your answers in numerical order (1a, 1b, ... 5).

Please answer in Finnish if possible, eli vastaa suomeksi jos vain osaat.

1. Answer and explain (6p)
a) Examples of VHDL-language structures that cannot be synthesized (never or
sometimes) (2p)
b) Show basic example (or two) how Mealy state machine can be implemented with
VHDL-language (2p)
c) What is the difference between loop-structures of programming language (like C)

and hardware description language (like VHDL)? (2p)

2: Analyze the code in the following page. The clock period is 10 ns. (9p)
a) What errors or suspicious structures there are in the code? (4p)
b) Fill in the timing diagram below directly according the code, i.e., without

correcting any errors. Present the timing as simulator interprets it. (5p)

 

 
Name:

Student no.

library ieee;

use ieee.std logic 1164.all;

use ieee.numeric std.all;
use std.textio.all;

entity tentti kl4 is

 

generic (
data width g integer := 8);
port (7 j
clk std logic;
rst n std logic;
ctrl in std logic;
val In std logic vector
sum out std logic vector
d out std logic;
eg out out std logic

end tentti k 14;

architecture gatelevel of tentti kl14 is

  

 

 

 

(data width g-1 downto 0);
(data width g-1 downto 0);

 

 

 

signal prev ctrl r = '0'; -— delay reg
signal edge W detect falling edge
signal sum r integer; -—- accumulate
begin etelin
mike process (clk, rst n) n N
variable sum integer;
begin
if rst n then
sum T <= 0; 4vl-
d out <= Pre
= vot
elsif clk'event and clk = ' then -
d out <= 10';
prev ctrl r <= ctrl in;
d out <= prev ctrl r; va
if edge = "1"! then
sum r <= to integer(unsigned (val in)) + sum r;
end if;
end if;
end process mike; mn
50 00*
sum out <= std logic vector (to unsigned (sum r, data width 9g)); Alo
patton process (val in, ctrl in, prev ctrl r, rst n)
begin vyt
if (prev ctrl r = '0' and ctrl in="1') then edge <= '1 Po ctel in
else edge <= '0'; s
end if; clin -—

if std logic vector
eg out <= "1!;

else
eg out <= "0";
end If; Som v
end process patton;
vela

end gatelevel;

(to unsigned (sum r, data width g))

val in then
Name:
Student no.
3. Analyze the VHDL code on the previous page. Show the resulting logic diagram after
RTL syntehsis.Use dashed line to show separate synthesized logic of each process.
Show every port, signal and variable. Don't make too small or ugly diagram, but clear
and elegant. (6p)
3. Explain (5p)
a) What is clock skew and how does it affect the FPGA's internal structure? (1p)
b) What happens when reading a signal that is currently at value 'Z'? (1p)
c) Why should entity's output be registered? (1p)
d) Is it a good or bad idea that the same person writes both the DUV and TB?
Why/why not? (1p)
e) What are 3 main delivery types of an IP component? (1p)
5. Analyze the circuit below. (4p)
a) Which signals have to be synchonized? Or is it necessary to synchronize any of
them? (2p)

b) Is there enough signals for proper working? (2p)