Exam text content

 

 

Name:
Student no.

==—111"

Final Exam: Answer every guestion
2nd Midterm Exam: Answer only guestions 4-6

Made by: Arto Perttula

Students can use any calculator or dictionary.

Moreover, each student can have 1 A4 sheet of own notes. There are no restrictions
about their style and they are not collected.

Students can do anything they wish with the exam paper.

In addition to text, use figures, tables, eguations, and examples in your answers.

In logic diagrams, you can use basic gates (AND, OR. ...), flip-flops, multiplexers, and common
arithmetic components (adder, subtractor, multiplier, comparator...).

Mark the name of every signal and indicate their width clearly.

Preferably write your answers in numerical order (1a, 1b, ... 6).

Please answer in Finnish if possible, eli vastaa suomeksi jos vain osaat.

1: Answer and explain (4p)
a) Terms: signal's event and delta delay (2p)
b) Whatis the difference between architecture types RTL and structural (2p)
2; State machines(4p)
a) Give an example how Mealy state machine differs from Moore state machine
(2p)
b) What are the basic styles to implement state machines with VHDL? What

differences there are in practice between them? (2p)

3. Analyze the code in the following page. The clock period is 10 ns. (7p)
a) What errors or suspicious structures there are in the code? (There is no syntax
errors) (3p)
b) Fill in the timing diagram below directly according the code, i.e., without

correcting any errors. Present the timing as simulator interprets it. (4p)

I 1
siin = ; i = | [ |

    
 
 
 
  

 

 

 

 

 

 

 

 

mtn < i
ctrl in |
val in 000 |.

 

 

Fill in the response)
 

Name:
Student no.

library ieee;

use ieee.std logic 1164.all;
use ieee.numeric std.all;

entity tentti is

generic (
data width g

Porta
clk in
rst n in
eI in in
val in in
c out out
d out out
e out out
) 7

end tentti;

architecture gatelevel of tentti is

signal ninja

begin

integer := 3);
std logic;
std logic;
std logic;
std logic vector
std logic;
std logic vector
std logic vector

(data width g-1 downto 0);

(data width g-1 downto 0);
(data width g-1 downto 0)

: unsigned ( data width g-1 downto 0);

tenho: process (ctrl in, ninja, val in)

begin
if ctr] in =
Sont <=
else
e out <=
end if;
end process

sauren

variable tmp v

11"
not val in after 4 ns;

then

val in after 4 ns;

tenho;

begin
if rst n = "0' then
ninjass- (others; "0")%
11"

elsif clk'event and clk =
:= ninjatl;
std logic vector(tmp v);

 

ninja <= ninja +2;

end if;

end process sauren;

process (ninja)
begin
if to integer

coat < "17

else

oat < 1017

end if;
end process;

==e Outs 05;

end gatelevel;

(ninja) = 6 then

: process (clk, rst n, ninja)
unsigned (3-1 downto

then
      

Name:

—f

ji Student no.

Analyze the VHDL code on the previous page. Show the resulting logic diagram after
RTL syntehsis.Use dashed line to show separate synthesized logic of each process.
Show every port, signal and variable. Don't make too small or ugly diagram, but clear
and elegant. (6p)

5. Clocking (4p)
a) What means the term clock domain? Draw a figure where it exists. What is the
result of it or is there any results? (2p)
b) Why would it be desirable to use many clock signals in the same chip? (2p)
5 Analyze the test circuit below (5p)
a) How the metastability is detected in basic RTL-simulation? (2p)
b) How the test circuit works? (Hint: in addition to text, draw a small timing diagram

where something interesting happens) (3P)

Figure 4. Test Circuit Structure for Metastability Characterization

Synchronization register
(Synchronizer chain of length 1)
f

     

 

error

clkb

Figure t5. Test Circuit